1. Technical Field
The present disclosure relates to nonvolatile memory devices, more particularly, to nonvolatile memory deices whose memory cells include variable resistive material.
2. Description of the Related Art
The bit data of DRAM (Dynamic RAM) and flash memory devices are usually determined by the level of charge stored in memory cells. However, in the case of some nonvolatile memory devices bit data can be determined by the level of current flowing through resistive materials of memory cells. These nonvolative memory devices include PRAM (Phase change Random Access Memory), RRAM (Resistive RAM), and MRAM (Magnetic RAM). The variable resistive material may be phase-change materials such as chalcogenide alloy (PRAM), or MTJ (Magnetic Tunnel Junction) thin films.
For example, PRAM changes phase-change material into a crystal state or an amorphous state through heating process. The phase-change material in the crystal state has a low resistance and is defined to retain bit data “0,” while the phase-change material in the amorphous status has high resistance, and is defined to retain bit data “1.”
FIG. 1 illustrates a conventional nonvolatile memory device.
Referring to FIG. 1, the conventional nonvolatile memory device includes multiple memory cell blocks BLK0, BLK1, multiple section word line driver blocks SWD_BLK0-SWD_BLK2, and multiple conjunction blocks CNJ0-CNJ2. Conjunction blocks are distinguished from multiple section word line driver blocks in that they are disposed adjacent to an input/output circuit whereas multiple section word line driver blocks are disposed adjacent to memory cell blocks.
Each of the memory cell blocks BLK0-BLK2 includes an array of nonvolatile memory cells. A main word line MWL is disposed across the multiple cell blocks BLK0-BLK2 and is coupled to each of the section word line driver blocks SWD_BLK0-SWD_BLK2. Each of the section word line driver blocks includes multiple section word line drivers, and each of the section word line drivers controls voltage level of corresponding multiple sub-word lines SWL00-SWLn0, SWL01-SWLn1 and SWL02-SWLn2 by responding to voltage level of the main word line and voltage levels of block select signal E00-En0, E01-En1 and E02-En2. Each of multiple sub-word lines SWL00-SWLn0, SWL01-SWLn1 and SWL02-SWLn2 is disposed across memory cell blocks and is coupled to corresponding multiple nonvolatile memory cells.
Each section word line driver pulls up the voltage level of the sub-word lines SWL00-SWLn0, SWL01-SWLn1 and SWL02-SWLn2 through pull-up elements U0-Un, and pulls down the voltage level of the sub-word lines SWL00-SWLn0, SWL01-SWLn1 and SWL02-SWLn2 through pull-down elements D0-Dn. The pull-up elements U0-Un can be PMOS transistors, and the pull-down elements D0-Dn can be NMOS transistors.
In conventional nonvolatile memory devices, the pull-up elements U0-Un and the pull-down elements D0-Dn operate by responding to the level of voltage applied to a main word line MWL. Selection elements S0-Sn, located in conjunction blocks CNJ0-CNJ2, are connected to each of the pull-down elements D0-Dn in series. The selection elements S0-Sn operate by responding to block select signals E00-En0, E01-En1, and E02-En2 which include block information provided by a block select signal generating circuit 10. The selection elements S0-Sn can be NMOS transistors. Since each sources node of the pull-down elements D0-Dn needs to be connected to each drain node of the pull-down elements S0-Sn, interconnecting lines may limit compact layout of the pull-down elements D0-Dn. Furthermore, the lengthy interconnection between pull-down elements D0-Dn and pull-down elements S0-Sn results in increased parasitic resistance R which deteriorates performance of nonvolatile memory devices.